The present invention relates to a Data Aligned Synchronous Link (DASL) interface for providing a high speed point-to-point serial data communication link. Specifically, a DASL interface is provided having a receiver which deserializes the received data in a manner which avoids inaccuracies due to phase jitter.
DASL links are utilized for providing high speed point-to-point interchange communication between CMOS ASIC modules. As most CMOS ASIC devices have an internal parallel data bus structure, it has been found advantageous to serialize the parallel data when transmitting the data from chip to chip to reduce the pin out requirement for the chips. Serial communication between the chips requires an interface to receive the data and deserialize the data into a parallel data format. In order to convert the serial format data into parallel format data, each of the received serial data bits is oversampled. The process of sampling each data bit requires a sampling time which is accurately linked to the synchronous data received so that an accurate assessment of the value of the data bit can be made.
In order to facilitate the accurate location of the sampling time, the apparatus and method described in the aforementioned related application provide for a training pattern to be sent between connected chips or modules so that the receiving module can develop bit synchronization with the incoming training pattern. Once the synchronization has been realized, it is then possible to begin transferring data between connected chips or modules and convert the data to a parallel format using the previously established sampling point.
The received serial data is, however subject to the effects of jitter, wherein data transmission edges appear to change with time. Sampling of the serial data signal must be done in a way which avoids any false detections due to the jitter of data transitions within the serial bit stream. The data transitions may change over time due to changes in operating conditions such as temperature, and the sampling points for sampling the serialized data must move to a new sample time position to avoid the consequences of environmentally induced jitter. Accordingly, the interface must perform a bit alignment so that sampling occurs essentially in the middle of a data bit rather than near its edges so that a reliable determination of the value of each data bit may be made. Resetting the sample time during the data mode operation must be done using received data which may have any random bit pattern requiring a different process for reestablishing the sampling time.
The present invention is directed to a process which determines an optimum sampling time for sampling bits of a serial data stream. During a data mode operation multiple samples of the data bits contained in the serial bit stream are received by a delay line where they are oversampled. Similar to the sampling point evaluation which took place during the training procedure, a bit edge mask is obtained for each of the sample data sequences by combining adjacent samples of the data stream in a logical operation which identifies within the samples of the received data bits the location of a data transition or change. Once all of the transition edges are located, sample times can be selected which lie between the transition edges on an accurate basis.
A number of sets of requests are made by the interface receiver to collect multiple samples of the data and create the bit edge masks for the samples of data which are used to create a delay line sample mask. Data transition edges are located and analyzed with respect to their location to the current sample point which was selected during the training procedure.
The system locates first and second edges of first and second consecutive bits currently being sampled in a delay line. Once the foregoing edges are located within the delay line, the current sample points, corresponding to a sample time for the receive interface, are evaluated by comparing their location with respect to the edges. A new optimal sample point for each of the bits can be recalculated, based on the positions of the newly located bit transition edges. In a preferred embodiment of the invention, the new optimal sampling points are integrated with respect to previously calculated sample points determined in response to earlier requests made by the receiver. When the integrated value exceeds a threshold value, the sampling points are reset to a new value which identifies a new sampling time for the receiver. Using the average of the new sample point locations further reduces the possibility of a sampling error due to phase jitter.